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dsPIC30F
4.0
DEVICE OVERVIEW FOR
Note:
The device depicted in Figure 4-1 is repre-
MOTOR CONTROL AND
POWER CONVERSION FAMILY
Figure 4-1 shows a sample device block diagram
typical of the dsPIC30F Motor Control Product Family.
Pin functionality and pinouts for this family are shown in
Appendix B.
sentative of this family. Other devices of
the same family may vary in terms of
number of pins and multiplexing of pin
functions. Typically, smaller devices in the
family contain a subset of the peripherals
present in the device(s) shown here.
FIGURE 4-1:
dsPIC30F6010A BLOCK DIAGRAM
Central Processing Unit
Y Data Bus
X Data Bus
16
16
16
16
Interrupt
Controller
PSV & Table
Data Access
24 Control Block
8
16
Data Latch
Y Data
RAM
(4 Kbytes)
Data Latch
X Data
RAM
(4 Kbytes)
16
24
Address
Latch
Address
Latch
Address Latch
Program Memory
(144 Kbytes)
23
PCU PCH  PCL
Program Counter
Stack Loop
Control Control
Logic Logic
16
Y AGU
16
X RAGU
X WAGU
16
Data EEPROM
(4 Kbytes)
Effective Address
Data Latch
16
System Integration
16
24
ROM Latch
IR
16
16 x 16
16
OSC1/CLKI
Timing
Generation
Instruction
Decode &
Control
Decode
W Reg Array
16 16
Power-up
Timer
Control Signals
to Various Blocks
DSP
Engine
Divide
Unit
Oscillator
Start-up Timer
POR/BOR
Reset
ALU<16>
MCLR
Watchdog
Timer
16
16
Low Voltage
V DD , V SS
Detect
AV DD , AV SS
Motor Control and Power Conversion Family Peripherals
CAN1,
CAN2
10-bit ADC
Input
Capture
Module
Output
Compare
Module
I 2 C?
I/ O Ports
A B C D E F G
SPI1,
SPI2
Timers
QEI
Motor Control
PWM
UART1,
UART2
? 2005 Microchip Technology Inc.
DS70043F-page 7
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